A frequency synthesizer composed of a PLL circuit is an important approach for generating clock signals. The frequency synthesizer inputs a low-frequency reference signal with high stability and high accuracy to output a series of high-frequency clock signals.
FIG. 1 is a schematic diagram of a conventional PLL circuit. The operating principle of the conventional PLL circuit is described below. A phase/frequency detector 3 uses a reference clock signal as a reference to compare a frequency and a phase of the reference clock signal with those of a feedback signal outputted from an output end of an N divider 8. Within an operating range of the phase/frequency detector 3, an error signal is generated when any phase (frequency) difference is detected. The error signal, which is directly proportional to a phase difference between the reference clock signal and the feedback signal, controls a charge pump 4 to output a charge pump signal. Alternating components of the charge pump signal are removed by a filter unit 5 to generate a voltage signal. With a voltage-to-current converting unit 6, the voltage signal is converted to a current signal to drive a current-controlled oscillator (CCO) 7 to reduce its frequency in a way that a phase/frequency difference of the current signal is decreased. The frequency of the PLL is then considered locked when phase or frequency difference between the reference clock signal and the feedback signal is reduced to zero.
PLL circuits are required to have good capabilities in restraining noise, which means that smaller loop bandwidth is needed to remove high-frequency noise. Meanwhile, PLL circuits are also expected to output rather high frequencies. The reference frequency is commonly generated by a crystal oscillator that can only handle a limited frequency of tens of MHz. Therefore, when a PLL circuit needs to output a high frequency in GHz, for example, an oscillator of the PLL circuit needs to provide a wider frequency range and a greater gain. According to a relationship that a gain of an oscillator is directly proportional to its loop bandwidth, a greater gain may result in a wider loop bandwidth of the PLL circuit, thus causing a failure in removing excessive noise and degrading the capability of restraining noise. In order to overcome a dilemma between the wide frequency range oscillator and the narrow loop bandwidth of the PLL circuit, a single-path PLL circuit and a PLL circuit with digital control have been developed. In a first solution, the single PLL circuit implements a filter capacitor with extremely large capacitance to reduce the loop bandwidth. In the second solution, the PLL circuit with digital control first selectively activates passive or active components of an oscillator to obtain an appropriate coarse-tuned frequency. When a frequency difference between a reference clock signal and a feedback signal is small enough, the PLL circuit with digital control is switched to a PLL control loop, which has smaller voltage control oscillator (VCO) gain, loop bandwidth and frequency range. Accordingly, the PLL circuit has a large tuning frequency range and a small loop bandwidth to meet requirements of high frequency and narrow bandwidth of a PLL circuit.
Although the foregoing two circuits overcome the dilemma between the wide frequency range and the narrow loop bandwidth to a certain extent, both of the circuits still have their disadvantages. A disadvantage of the single-path PLL circuit is that product cost is increased for the reason that the filter capacitor has to be designed as an off-chip capacitor since it is too large to be integrated into an integrated circuit (IC). A disadvantage of the PLL circuit with digital control is that it can not keep track of and adapt to variations of temperature or technique variables. When the temperature or technique variables are modified, the PLL circuit with digital control needs to be periodically switched to lock to the coarse-tuned frequency due to the small tuning frequency range of the PLL control loop, such that not only design complexity of the digital control PLL circuit is increased but also accuracy is reduced.
A main object of the present invention is to provide a dual PLL circuit and a method for controlling the same to solve the foregoing problems.